Future computing platforms have a high chance of being heterogeneous, where superconducting chips (i.e. analogous to a classical CPU) are interconnected to neutral atom computers (i.e. analogous to classical RAM), for example. This means that QEC and fault-tolerance-protocols, on the one hand, and algorithms/circuits, on the other hand, influence each other through the architecture of the computer. In the first part of this talk, we present our compilation framework addressing heterogeneous architectures. In the second part, we focus on the challenge of interconnects: the probability of physical qubit loss might become a performance bottleneck. To this end, we investigate how physical defects in surface-code (SC) lattices affect the placement and reliability of logical operator measurements performed on the superconducting part of the heterogeneous computer. While SC on ideal lattices have families of equivalent logical observables related by stabilizer multiplication, imperfect lattices break this equivalence. We introduce a simple yet general defect model for unrotated surface-code patches. The model is used to systematically benchmark logical error rates as a function of defect size and position under circuit-level depolarizing noise. We present also preliminary results on the analysis of bicycle bivariate QEC codes which are assumed to be used on the neutral atom part.