Our results outline a new benchmark for quantum performance:

• A 40-hour averaged two-qubit CZ gate fidelity of 99.93%
• Average simultaneous readout fidelity of 99.94 for both qubits in 280 ns readout duration
• Highest ever reported maximum fidelity for CZ gates 99,95%
• Single-qubit gate fidelities exceeding 99.98%

We achieved the results through a holistic optimization strategy, enabled by:

• Building quantum chips with precisely targeted qubit-coupler coupling strengths, which are based on numerical optimization to balance hybridization-induced crosstalk and incoherent gate errors.
• Introducing the novel Phase-Averaged Leakage Error Amplification (PALEA) protocol, which allows for precise calibration of coherent over- and under-rotation errors in the |11⟩–|02⟩ subspace, naturally arising due to the implementation of CZ gates used on all IQM devices. PALEA systematically reduces |2> leakage induced by a CZ gate by at least a factor of two compared to standard methods, simplifying calibration and enhancing compatibility with quantum error correction codes.
• Implementing a robust readout configuration featuring individual Purcell filters and shelving techniques. This enables high-fidelity, fast readout by transferring the |1⟩ state to |2⟩, increasing its effective readout lifetime.

Summing single-qubit, two-qubit, and readout errors together, we reach an impressive system-level error of 2.1 x 10^-3. Importantly, this device architecture and control methodology are compatible with scalable layouts, including the square-grid architectures essential for surface code implementations, paving a clear path to real-world quantum error correction.

Dive into the details of our pioneering work on quantum fidelity and its implications for quantum computing’s future!